View LTC3412EUF_4677165.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3412 1 3412fb the ltc ? 3412 is a high efficiency monolithic synchro- nous, step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.625v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 2.5a of output current. the internal synchronous power switch with 85m on-resistance increases efficiency and eliminates the need for an exter- nal schottky diode. switching frequency is set by an external resistor or can be sychronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. opti-loop ? compensation allows the transient response to be opti- mized over a wide range of loads and output capacitors. the ltc3412 can be configured for either burst mode ? operation or forced continuous operation. forced con- tinuous operation reduces noise and rf interference while burst mode operation provides high efficiency by reduc- ing gate charge losses at light loads. in burst mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. to further maximize battery life, the p-channel mosfet is turned on continu- ously in dropout (100% duty cycle). portable instruments battery-powered equipment notebook computers distributed power systems cellular telephones digital cameras high efficiency: up to 95% 2.5a output current low quiescent current: 62 a low r ds(on) internal switches: 85m programmable frequency: 300khz to 4mhz no schottky diode required 2% output voltage accuracy 0.8v reference allows low output voltage selectable forced continuous/burst mode operation with adjustable burst clamp synchronizable switching frequency low dropout operation: 100% duty cycle power good output voltage monitor overtemperature protection available in 16-lead thermally enhanced tssop and qfn packages 2.5a, 4mhz, monolithic synchronous step-down regulator figure 1. 2.5v, 2.5a step-down regulator efficiency vs load current sv in pv in pgood sw ltc3412 pgnd sgnd run/ss 309k v in 2.7v to 5.5v 1000pf r t i th v fb sync/mode 1 h 4.7m 470pf 75k 100pf 100 f v out 2.5v 2.5a 15k 110k 392k 22 f 3412 f01 load current (a) 0.001 efficiency (%) 100 80 60 40 20 0 10 3412 g01 v in = 3.3v v out = 2.5v burst mode operation forced continuous 0.1 1 0.01 descriptio u features applicatio s u typical applicatio u , lt, ltc, ltm, burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc3412 2 3412fb input supply voltage ...................................e 0.3v to 6v i th , run, v fb voltages ............................... e 0.3v to v in sync/mode voltages ................................ e 0.3v to v in sw voltage ................................... e 0.3v to (v in + 0.3v) peak sw sink and source current ......................... 6.5a order part number consult ltc marketing for parts specified with wider operating temperature ranges. ltc3412efe ltc3412ife absolute axi u rati gs w ww u package/order i for atio uu w (note 1) 1 2 3 4 5 6 7 8 top view fe package 16-lead plastic tssop 16 15 14 13 12 11 10 9 sv in pgood i th v fb r t sync/mode run/ss sgnd pv in sw sw pgnd pgnd sw sw pv in 17 fe part marking 3412efe 3412ife exposed pad (pin 17) is sgnd, must be soldered to pcb t jmax = 125 c, e ja = 37.6 c/w, e jc = 10 c/w operating temperature range (note 2) ....................................... e 40 c to 85 c junction temperature (note 5) ............................. 125 c lead temperature (soldering, 10 sec) tssop .............................................................. 300 c order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ order part number LTC3412EUF uf part marking 3412 exposed pad (pin 17) is sgnd, must be soldered to pcb t jmax = 125 c, e ja = 34 c/w, e jc = 1 c/w 16 15 14 13 5 6 7 8 top view 17 uf package 16-lead (4mm 4mm) plastic qfn 9 10 11 12 4 3 2 1 run/ss sgnd pv in sw pgood sv in pv in sw sync/mode r t v fb i th sw pgnd pgnd sw electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v unless otherwise specified. symbol parameter conditions min typ max units sv in signal input voltage range 2.625 5.5 v v fb regulated feedback voltage (note 3) 0.784 0.800 0.816 v i fb voltage feedback leakage current 0.1 0.4 + a 6 v fb reference voltage line regulation v in = 2.7v to 5.5v (note 3) 0.04 0.2 %/v v loadreg output voltage load regulation measured in servo loop, v ith = 0.36v 0.02 0.2 % measured in servo loop, v ith = 0.84v e 0.02 e 0.2 % 6 v pgood power good range 7.5 9% r pgood power good pull-down resistance 120 200 1 i q input dc bias current (note 4) active current v fb = 0.78v, v ith = 1v 250 330 + a sleep v fb = 1v, v ith = 0v 62 80 + a shutdown v run = 0v, v mode = 0v 0.02 1 + a
ltc3412 3 3412fb typical perfor a ce characteristics uw efficiency vs load current efficiency vs load current efficiency vs load current load current (a) 0.001 efficiency (%) 100 80 60 40 20 0 10 3412 g01 v in = 3.3v v out = 2.5v burst mode operation forced continuous 0.1 1 0.01 100 90 80 70 60 50 40 30 20 10 0 load current (a) 0.001 efficiency (%) 10 3412 g02 v out = 2.5v 1mhz burst mode operation 0.1 1 0.01 v in = 3.3v v in = 5v load current (a) 0.001 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 10 3412 g03 v out = 2.5v 1mhz forced continuous 0.1 1 0.01 v in = 3.3v v in = 5v electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 3.3v unless otherwise specified. symbol parameter conditions min typ max units f osc switching frequency r osc = 309k 0.88 0.95 1.1 mhz switching frequency range (note 6) 0.3 4 mhz f sync sync capture range (note 6) 0.3 4 mhz r pfet r ds(on) of p-channel fet i sw = 1a (note 7) 85 110 m r nfet r ds(on) of n-channel fet i sw = C1a (note 7) 65 90 m i limit peak current limit 4 5.4 a v uvlo undervoltage lockout threshold 2.375 2.500 2.625 v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 1 a v run run threshold 0.5 0.65 0.8 v i run run/ss leakage current 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3412e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3412i is guaranteed to meet specified performance over the C 40 c to 85 c temperature range. note 3: the ltc3412 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and power dissipation as follows: ltc3412: t j = t a + p d (37.6 c/w). note 6: 4mhz operation is guaranteed by design and not production tested. note 7: switch on resistance is guaranteed by design and test correlation in the uf package and by production test in the fe package.
ltc3412 4 3412fb input voltage (v) 2.55 3.05 3.55 4.05 4.55 5.05 efficiency (%) 98 96 94 92 90 88 86 3412 g04 v out = 2.5v 1mhz burst mode operation load = 100ma load = 1a load = 2.5a frequency (khz) 300 800 1300 1800 2300 2800 3300 3800 efficiency (%) 97 96 95 94 93 92 91 3412 g05 v in = 3.3v v out = 2.5v load = 1a burst mode operation 1 h 0.47 h 2.2 h load current (a) 0 0.5 1 1.5 2 2.5 % v out /v out 0.02 0.00 C0.02 C0.04 C0.06 C0.08 C0.10 C0.12 C0.14 C0.16 C0.18 3412 g06 v in = 3.3v v out = 2.5v 4 s/div v out 20mv/div i l 200ma/div 3412 g07 20 s/div 3412 g08 v out 100mv/div i l 1a/div 20 s/div 3412 g09 v out 100mv/div i l 1a/div efficiency vs frequency efficiency vs input voltage load regulation load step transient forced continuous burst mode operation load step transient burst mode operation v in = 3.3v, v out = 2.5v load = 50ma v in = 3.3v, v out = 2.5v load step = no load to 2.5a v in = 3.3v, v out = 2.5v load step = 50ma to 2.5a typical perfor a ce characteristics uw temperature ( c) C45 C25 C5 15 35 55 75 95 115 120 reference voltage (v) 3412 g11 0.7960 0.7955 0.7950 0.7945 0.7940 0.7935 0.7930 0.7925 0.7920 v in = 3.3v input voltage (v) 2.5 3 3.5 4 4.5 5 on-resistance (m ) 3412 g12 120 100 80 60 40 20 0 pfet on-resistance nfet on-resistance start-up, burst mode operation reference voltage vs temperature switch on-resistance vs input voltage 1ms/div 3412 g10 v out 1v/div v run 1v/div i l 1a/div v in = 3.3v, v out = 2.5v load = 1
ltc3412 5 3412fb temperature ( c) C40 C20 0 20 40 60 80 100 120 on-resistance (m ) 3412 g13 120 110 100 90 80 70 60 50 40 30 20 v in = 3.3v pfet on-resistance nfet on-resistance input voltage (v) 2.5 3 3.5 4 4.5 5 5.5 leakage current (na) 3412 g14 2.5 2.0 1.5 1.0 0.5 0 main switch synchronous switch r osc (k ) 50 150 250 350 450 550 650 750 850 950 frequency (khz) 3412 g15 4500 4000 3500 3000 2500 2000 1500 1000 500 0 v in = 3.3v input voltage (v) 2.5 3 3.5 4 4.5 5 5.5 frequency (khz) 3412 g16 1050 1040 1030 1020 1010 1000 990 r = 309k temperature ( c) C40 C20 0 20 40 60 80 100 120 frequency (khz) 3412 g17 1010 1008 1006 1004 1002 1000 998 996 994 992 990 v in = 3.3v input voltage (v) 2.5 3 3.5 4 4.5 5 5.5 dc supply current ( a) 3412 g18 350 300 250 200 150 100 50 sleep active typical perfor a ce characteristics uw switch on-resistance vs temperature switch leakage vs input voltage frequency vs r osc frequency vs input voltage switching frequency vs temperature dc supply current vs input voltage supply current ( a) 350 300 250 200 150 100 50 0 temperature ( c) C40 C20 0 20 40 60 80 100 120 3412 g19 v in = 3.3v active sleep burst clamp voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 minimum peak inductor current (ma) 3412 g20 4000 3500 3000 2500 2000 1500 1000 500 0 v in = 3.3v dc supply current vs temperature minimum peak inductor current vs burst clamp voltage input voltage (v) 2.75 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 4.25 5.25 3412 g21 3.25 3.75 4.75 current limit (a) current limit vs input voltage
ltc3412 6 3412fb pi fu ctio s uuu sv in (pin 1/pin 11): signal input supply. decouple this pin to sgnd with a capacitor. normally sv in is equal to pv in . sv in can be greater than pv in but keep the voltage difference between sv in and pv in less than 0.5v. pgood (pin 2/pin 12): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. i th (pin 3/pin 13): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.2v corresponding to the zero-sense voltage (zero current). v fb (pin 4/pin 14): feedback pin. receives the feedback voltage from a resistive divider connected across the output. r t (pin 5/pin 15): oscillator resistor input. connecting a resistor to ground from this pin sets the switching fre- quency. sync/mode (pin 6/pin 16): mode select and external clock synchronization input. to select forced continuous, tie to sv in . connecting this pin to a voltage between 0v and 1v selects burst mode operation with the burst clamp set to the pin voltage. run/ss (pin 7/pin 1): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3412. in shutdown all functions are disabled drawing < 1 a of supply current. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 8/pin 2): signal ground. all small-signal components, compensation components and the exposed pad on the bottom side of the ic should connect to this ground, which in turn connects to pgnd at one point. pv in (pins 9, 16/pins 3, 10): power input supply. decouple this pin to pgnd with a capacitor. sw (pins 10, 11, 14, 15/pins 4, 5, 8, 9): switch node connection to the inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. pgnd (pins 12, 13/pins 6, 7): power ground. connect this pin close to the (C) terminal of c in and c out . exposed pad (pin 17/pin 17): signal ground. must be soldered to pcb for electrical connection and thermal performance. (fe/uh package)
ltc3412 7 3412fb C + 2 7 4 C + + C C + 0.74v error amplifier sync/mode burst comparator bclamp nmos current comparator pmos current comparator reverse current comparator 0.86v run run/ss 15 13 12 14 11 sw p-ch n-ch 10 pgood 3 i th v fb 0.8v 5 r t 6 sync/mode 3412 fbd 16 pv in 9 8 sgnd 1 sv in slope compensation voltage reference oscillator logic slope compensation recovery C + C + + C pgnd + C fu ctio al block diagra uu w operatio u main control loop the ltc3412 is a monolithic, constant-frequency, current mode step-down dc/dc converter. during normal opera- tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error amplifier adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C2a for forced continuous mode and 0a for burst mode operation. the operating frequency is set by an external resistor connected between the r t pin and ground. the practical switching frequency can range from 300khz to 4mhz.
ltc3412 8 3412fb operatio u overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mos- fet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. forced continuous mode connecting the sync/mode pin to sv in will disable burst mode operation and force continuous current operation. at light loads, forced continuous mode operation is less efficient than burst mode operation but may be desirable in some applications where it is necessary to keep switch- ing harmonics out of a signal band. the output voltage ripple is minimized in this mode. burst mode operation connecting the sync/mode pin to a voltage between 0v to 1v enables burst mode operation. in burst mode operation, the internal power mosfets operate intermit- tently at light loads. this increases efficiency by minimiz- ing switching losses. during burst mode operation, the minimum peak inductor current is externally set by the voltage on the sync/mode pin and the voltage on the i th pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the i th pin drops. as the i th voltage falls below 150mv, the burst comparator trips and enables sleep mode. during sleep mode, the top mosfet is held off and the i th pin is disconnected from the output of the error amplifier. the majority of the internal circuitry is also turned off to reduce the quiescent current to 62 a while the load current is solely supplied by the output capacitor. when the output voltage drops, the i th pin is reconnected to the output of the error amplifier and the top power mosfet along with all the internal circuitry is switched back on. this process repeats at a rate that is dependent on the load demand. pulse skipping operation can be implemented by connect- ing the sync/mode pin to ground. this forces the burst clamp level to be at 0v. as the load current decreases, the peak inductor current will be determined by the voltage on the i th pin until the i th voltage drops below 200mv. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. frequency synchronization the internal oscillator of the ltc3412 can be synchronized to an external clock connected to the sync/mode pin. the frequency of the external clock can be in the range of 300khz to 4mhz. for this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. during synchronization, the burst clamp is set to 0v and each switching cycle begins at the falling edge of the external clock signal. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maxi- mum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3412 is designed to operate down to an input supply voltage of 2.625v. one important consideration at low input supply voltages is that the r ds(on) of the p- channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3412 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished
ltc3412 9 3412fb operatio u internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3412, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. this keeps the maximum output current relatively constant regardless of duty cycle. short-circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases larger than 4.8a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current falls to a safe level. applicatio s i for atio wu u u the basic ltc3412 application circuit is shown in fig- ure 1. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge and switching losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3412 is determined by an external resistor that is connected between the r t pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r fhz k osc = ? 323 10 10 11 .? () () although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3412 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 ? 110ns ? f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. = ? ? ? ? ? ? ? ? ? ? ? ? ? i v fl v v l out out in 1 having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. high- est efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v fi v v out lmax out in max = ? ? ? ? ? ? ? ? ? ? ? ? ? () () 1 the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower induc- tance values will cause the burst frequency to increase.
ltc3412 10 3412fb inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, mollypermalloy, or kool m ? cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance re- quires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy mate- rials are small and dont radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko and sumida. c in and c out selection the input capacitance, c in , is needed to filter the trapezoi- dal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by: ii v v v v rms out max out in in out = ? () 1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not applicatio s i for atio wu u u offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher tempera- ture than required. several capacitors may also be paral- leled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: ?? + ? ? ? ? ? ? v i esr fc out l out 1 8 the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special poly- mer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capaci- tors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and
ltc3412 11 3412fb current to remain equal to i burst regardless of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the i th pin will decrease. when the i th voltage drops to 150mv, sleep mode is enabled in which both power mosfets are shut off along with most of the circuitry to minimize power consumption. all circuitry is turned back on and the power mosfets begin switching again when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple in- crease. the burst clamp voltage, v burst , can be set by a resistor divider from the v fb pin to the sgnd pin as shown in figure 1. pulse skipping, which is a compromise between low out- put voltage ripple and efficiency, can be implemented by connecting the sync/mode pin to ground. this sets i burst to 0a. in this condition, the peak inductor current is limited by the minimum on-time of the current comparator, and the lowest output voltage ripple is achieved while still op- erating discontinuously. during very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. frequency synchronization the ltc3412s internal oscillator can be synchronized to an external clock signal. during synchronization, the top mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 4mhz. synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. because slope compensation is generated by the oscillators rc circuit, the external fre- quency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. soft-start the run/ss pin provides a means to shut down the ltc3412 as well as a timer for soft-start. pulling the run/ss pin below 0.5v places the ltc3412 in a low quiescent current shutdown state (i q < 1 a). applicatio s i for atio wu u u the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the output voltage is set by an external resistive divider according to the following equation: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 2. figure 2. setting the output voltage ltc3412 v fb v out sgnd 3412 f02 r2 r1 burst clamp programming if the voltage on the sync/mode pin is less than v in by 1v, burst mode operation is enabled. during burst mode operation, the voltage on the sync/mode pin determines the burst clamp level which sets the minimum peak inductor current, i burst , for each switching cycle accord- ing to the following equation: iv v a v burst burst = ? () ? ? ? ? ? ? 02 375 08 . . . v burst is the voltage on the sync/mode pin. i burst can be programmed in the range of 0a to 3.75a. for values of v burst greater than 1v, i burst is set at 3.75a. for values of v burst less than 0.2v, i burst is set at 0a. as the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor
ltc3412 12 3412fb the ltc3412 contains an internal soft-start clamp that gradually raises the clamp on i th after the run/ss pin is pulled above 2v. the full current range becomes available on i th after 1024 switching cycles. if a longer soft-start period is desired, the clamp on i th can be set externally with a resistor and capacitor on the run/ss pin as shown in figure 1. the soft-start duration can be calculated by using the following formula: trc v vv seconds ss ss ss in in = ? ? ? ? ? ? ? () ln . 18 efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg =f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in con- tinuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3412 does not dissipate much heat due to its high efficiency. but, in applications where the ltc3412 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction tempera- ture reaches approximately 150 c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3412 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. applicatio s i for atio wu u u
ltc3412 13 3412fb the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3412 in dropout at an input voltage of 3.3v, a load current of 2.5a and an ambient temperature of 70 c. from the typical perfor- mance graph of switch resistance, the r ds(on) of the p- channel switch at 70 c is approximately 97m . there- fore, power dissipated by the part is: p d = (i load 2 )(r ds(on) ) = (2.5a) 2 (97m ) = 0.61w for the tssop package, the ja is 37.6 c/w. thus the junction temperature of the regulator is: t j = 70 c + (0.61w)(37.6 c/w) = 93 c which is below the maximum junction temperature of 125 c. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. the i th pin external components and output capaci- tor shown in figure 1 will provide adequate compensation for most applications. design example as a design example, consider using the ltc3412 in an application with the following specifications: v in = 2.7v to 4.2v, v out = 2.5v, i out(max) = 2.5a, i out(min) = 10ma, f = 1mhz. because efficiency is important at both high and low load current, burst mode operation will be utilized. first, calculate the timing resistor: rkk osc = ? = 323 10 110 10 313 11 6 .? ? use a standard value of 309k. next, calculate the inductor value for about 40% ripple current at maximum v in : l v mhz a v v h = ? ? ? ? ? ? ? ? ? ? ? ? ? = 25 11 1 25 42 101 . ()() . . . using a 1 h inductor, results in a maximum ripple current of: = ? ? ? ? ? ? ? ? ? ? ? ? ? = i v mhz h v v a l 25 11 1 25 42 101 . ()() . . . c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. in this application, two tantalum capacitors will be used to provide the bulk capacitance and a ceramic capacitor in parallel to lower the total effective esr. for this design, two 100 f tantalum capacitors in parallel with a 10 f ceramic capacitor will be used. c in should be sized for a maximum current rating of: ia v v v v a rms rms = () ? ? ? ? ? ? ? = 25 25 42 42 25 1123 . . . . . . decoupling the pv in and sv in pins with a 22 f ceramic capacitor and a 220 f tantalum capacitor is adequate for most applications. the burst clamp and output voltage can now be pro- grammed by choosing the values of r1, r2 and r3. the voltage on the mode pin will be set to 0.32v by the resistor divider consisting of r2 and r3. a burst clamp voltage of 0.32v will set the minimum inductor current, i burst , as follows: ivv v v ma burst = ? () ? ? ? ? ? ? = 032 02 375 08 563 .. . . applicatio s i for atio wu u u
ltc3412 14 3412fb applicatio s i for atio wu u u if we set the sum of r2 and r3 to 185k, then the following equations can be solved: rr k r r v v 2 3 185 1 2 3 08 032 += += . . the last two equations shown result in the following values for r2 and r3: r2 = 110k , r3 = 75k. the value of r1 can now be determined by solving the equation shown below: 1 1 185 25 08 1 393 += = r k v v rk . . a value of 392k will be selected for r1. figure 4 shows the complete schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3412. check the following in your layout. 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3412. the exposed pad should be connected to sgnd. 2. connect the (+) terminal of the input capacitor(s), c in , as close as possible to the pv in pin. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd, or any other dc rail in your system). 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. figure 3. ltc3412 layout diagram top side bottom side
ltc3412 15 3412fb applicatio s i for atio wu u u figure 4. single lithium-ion to 2.5v, 2.5a regulator at 1mhz, burst mode operation using poscaps 8 sgnd c ss 470pf x7r c c 100pf * ** ? ?? toko d62cb a920cy-1rom sanyo poscap 4tpb100m taiyo yuden lmk325bj106mn sanyo poscap 2r5tpc220m 7 r ss 4.7m run 6 sync/mode r osc 309k 5 r t r2 110k 4 r3 75k v fb r ith 7.15k 3 c ith 680pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 l1* 1 h pgnd 14 sw 15 sw 16 pv in c in2 22 f x5r 6.3v c in1 ?? 220 f c out2 ? 10 f c out1 ** 100 f 2 v out 2.5v 2.5a v in 2.7v to 4.2v gnd 3412 f04 r1 392k + r pg 100k c fb 22pf x5r
ltc3412 16 3412fb 2.5v, 2.5a regulator using all ceramic capacitors 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode r osc 309k 5 r t r2 110k 4 r3 75k v fb r ith 15k 3 c ith 1000pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 l1* 1 h pgnd 14 sw 15 sw 16 pv in c1 22pf x5r c in2 22 f x5r 6.3v c in1 22 f x5r 6.3v c out ** 100 f v out 2.5v 2.5a v in 2.7v to 5.5v gnd 3412 f05 c in3 ** 100 f r1 392k * ** toko d62cb a920cy-1rom tdk c4532x5r0j107m c c 100pf r pg 100k 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode r osc 309k 5 r t r2 110k r3 75k 4 v fb r ith 10k 3 c ith 560pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 pgnd 14 sw 15 sw 16 pv in c in2 22 f** c in1 ** 22 f c out ** 22 f 2 v out 1.8v 2a v in 3.3v gnd r1 232k 3412 ta05 l1 1 h* * ** sumida cr431r0 avx 12066d226mat c2 47pf c1 22pf x5r r pg 100k 1.8v, 2.5a step-down regulator at 1mhz, burst mode operation typical applicatio s u
ltc3412 17 3412fb typical applicatio s u 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode r osc 137k 5 r t r2 182k 4 v fb r ith 22.1k 3 c ith 1000pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 pgnd 14 sw 15 sw 16 pv in c in2 100 f** c in1 ** 100 f c out ** 100 f 2 v out 2.5v 2.5a v in 3.3v gnd r1 392k r in 5 3412 ta06 l1 0.47 h* * ** vishay dale ihlp-2525cz-01 0.47 tdk c4532x5r0j107m c1 56pf c ff 22pf x7r r pg 100k c in3 0.1 f x5r 2.5v, 2.5a low output noise regulator at 2mhz load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3412 ta07 30 20 10 0 90 100 efficiency vs load current 2mhz, low noise
ltc3412 18 3412fb 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode r osc 309k 5 r t r2 200k 4 v fb r ith 15k 3 c ith 1000pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 pgnd 14 sw 15 sw 16 pv in c in2 22 f x5r 6.3v c in1 22 f x5r 6.3v c out ** 100 f v out 3.3v 2.5a v in 5v gnd r1 634k 3412 ta01 l1* 1 h * ** pulse p1166.162t tdk c4532x5r0j107m c c 100pf c1 22pf x5r c in3 ** 100 f r pg 100k 3.3v, 2.5a step-down regulator at 1mhz, forced continuous mode operation typical applicatio s u 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode r osc 309k 5 r t r2 110k 4 r3 75k v fb r ith 15k 3 c ith 1000pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 l1* 2 h m1 siliconix si2302ds d1 diodes, inc. b320a pgnd 14 sw 15 sw 16 pv in c1 22pf c in2 22 f x5r 6.3v c in1 22 f x5r 6.3v c out ** 100 f v out 3.3v v in 2.7v to 4.2v gnd gnd 3412 f04 c in3 ** 100 f 2 r1 576k * ** toko d63cb tdk c4532x5r0j107m c2 100pf r pg 100k v in maximum i out 2.7v 800ma 3v 900ma 3.5v 1.05a 4.2v 1.2a lithium-ion to 3.3v, single inductor buck-boost converter
ltc3412 19 3412fb package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ba fe16 (ba) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc uf package 16-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1692) 4.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wggc) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.55 0.20 16 15 1 2 bottom viewexposed pad 2.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.30 0.05 0.65 bsc 0.200 ref 0.00 C 0.05 (uf16) qfn 1004 recommended solder pad pitch and dimensions 0.72 0.05 0.30 0.05 0.65 bsc 2.15 0.05 (4 sides) 2.90 0.05 4.35 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer
ltc3412 20 3412fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2002 lt 0707 rev b ?printed in usa related parts typical applicatio u part number description comments ltc1701/ltc1701b 700ma (i out ), 1mhz step-down converter v in = 2.5v to 5v, b version: burst mode defeat, thinsot tm ltc1772/ltc1772b constant 550khz current mode step-down dc/dc controller v in = 2.5v to 9.8v, 94% efficiency, 100% duty cycle, thinsot ltc1773 constant frequency 550khz step-down dc/dc controller v in = 2.65v to 8.5v, 95% efficiency, v out from 0.8v to v in , msop-10 ltc1875 1.5a (i out ), 500khz synchronous step-down converter v in = 2.65v to 6v, 95% efficiency, pll, ssop-16 ltc1877 600ma (i out ), 500khz synchronous step-down converter v in = 2.65v to 10v, 95% efficiency, msop-8 ltc1878 600ma (i out ), 550khz synchronous step-down converter v in = 2.65v to 6v, 95% efficiency, msop-8 ltc1879 1.2a (i out ), 550khz synchronous step-down converter v in = 2.65v to 10v, 95% efficiency, ssop-16 ltc3404 600ma (i out ), 1.4mhz synchronous step-down converter v in = 2.65v to 6v, 95% efficiency, msop-8 ltc3405a 300ma (i out ), 1.5mhz synchronous step-down converter v in = 2.65v to 6v, 96% efficiency, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz synchronous step-down converter v in = 2.5v to 5.5v, 95% efficiency, thinsot, b version: burst mode defeat ltc3411 1.25a (i out ), 4mhz synchronous step-down converter v in = 2.5v to 5.5v, 95% efficiency, msop-10 thinsot is a trademark of linear technology corporation. 2.5v, 2.5a step-down regulator synchronized to 1.25mhz 8 sgnd c ss 470pf x7r 7 r ss 4.7m run 6 sync/mode 1.25mhz ext clock r osc 309k 5 r t r2 182k 4 v fb r ith 15k r pg 100k 3 c ith 1000pf x7r i th 2 pgood pgood 1 sv in 9 pv in 10 sw 11 sw 12 pgnd ltc3412 13 l1* 1 h pgnd 14 sw 15 sw 16 pv in c in2 22 f x5r 6.3v c in1 22 f x5r 6.3v c out1 ** 100 f v out 2.5v 2.5a v in 2.7v to 5.5v gnd r1 392k 3412 ta02 * ** toko d62cb a920cy-1rom tdk c4532x5r0j107m c c 100pf c1 22pf x5r c in3 ** 100 f

▲Up To Search▲

Price & Availability of LTC3412EUF

	To Download LTC3412EUF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .